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IDT74FCT2573AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS OCTAL TRANSPARENT LATCH
IDT74FCT2573AT/CT
FEATURES:
* * * * * * * *
DESCRIPTION:
A and C grades Low input and output leakage 1A (max.) CMOS power levels True TTL input and output compatibility: - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) Resistor outputs (-15mA IOH, 12mA IOL) Meets or exceeds JEDEC standard 18 specifications Reduced system switching noise Available in SOIC, QSOP, and TSSOP packages
The FCT2573T is an octal transparent latch built using advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is high. When LE is low, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is low. When OE is high, the bus output is in the high-impedance state. The FCT2573T has balanced drive outputs with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. The FCT2573T parts are plug-in replacements for FCT573T parts.
FUNCTIONAL BLOCK DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D O G
D O G
D O G
D O G
D O G
D O G
D O G
D O G
LE
OE O0 O1 O2 O3 O4 O5 O6 O7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
JUNE 2002
DSC-5499/2
(c) 2002 Integrated Device Technology, Inc.
IDT74FCT2573AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to +7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA VTERM(3) TSTG IOUT
OE D0 D1 D2 D3 D4 D5 D6 D7 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC O0 O1 O2 O3 O4 O5 O6 O7 LE
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF
NOTE: 1. This parameter is measured at characterization but not tested.
SOIC/ QSOP/ TSSOP TOP VIEW
PIN DESCRIPTION
Pin Names Dx LE OE Ox Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) 3-State Outputs Description
FUNCTION TABLE(1)
Dx H L X Inputs LE H H X OE L L H Outputs Ox L H Z
NOTE: 1. H = HIGH Voltage Level X = Don't Care L = LOW Voltage Level Z = High Impedance
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IDT74FCT2573AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 5%
Symbol VIH VIL IIH IIL IOZH IOZL II VIK VH ICC Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) High Impedance Output Current (3-State output pins)(4) Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = Max., VI = VCC (Max.) VCC = Min, IIN = -18mA -- VCC = Max., VIN = GND or VCC Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max VI = 2.7V VI = 0.5V VO = 2.7V VO = 0.5V Min. 2 -- -- -- -- -- -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -0.7 200 0.01 Max. -- 0.8 1 1 1 1 1 -1.2 -- 1 A V mV mA Unit V V A A A
OUTPUT DRIVE CHARACTERISTICS
Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3) VCC = Min IOH = -15mA VIN = VIH or VIL VCC = Min IOL = 12mA VIN = VIH or VIL Min. 16 -16 2.4 -- Typ.(2) 48 -48 3.3 0.3 Max. -- -- -- 0.5 Unit mA mA V V
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C.
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IDT74FCT2573AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle OE = GND LE = VCC One Bit Toggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle OE = GND LE = VCC Eight Bits Toggling VIN = VCC VIN = GND Test Conditions(1) Min. -- -- Typ.(2) 0.5 0.06 Max. 2 0.12 Unit mA mA/ MHz
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
0.6
2.2
mA
--
0.9
3.2
VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
1.2
3.4(5)
--
3.2
11.4(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2+ fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz.
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IDT74FCT2573AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW Parameter Propagation Delay Dx to Ox Propagation Delay LE to Ox Output Enable Time Output Disable Time Set-up Time, HIGH or LOW Dx to LE Hold Time, HIGH or LOW Dx to LE LE Pulse Width HIGH(3) Condition(1) CL = 50pF RL = 500 FCT2573AT Min.(2) Max. 1.5 5.2 2 1.5 1.5 2 1.5 5 8.5 6.5 5.5 -- -- -- FCT2573CT Min.(2) Max. 1.5 4.2 2 1.5 1.5 2 1.5 5 5.5 5.5 5 -- -- -- Unit ns ns ns ns ns ns ns
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested.
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IDT74FCT2573AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 7.0V 500 VIN Pulse G enerator D.U.T. 50pF R
T
SWITCH POSITION
Test Switch Closed Open Open Drain Disable Low Enable Low All Other Tests
V OU T
500 C
L
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal link
Test Circuits for All Outputs
DATA INPUT tSU TIMING INPUT ASYNCHRO NOUS CONTROL PRESET CLEAR ETC. SYNCHRON OUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
Octal link
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIG H PULSE
Octal link
1.5V
1.5V
tSU
tH
Pulse Width
Set-Up, Hold, and Release Times
ENABLE SAM E PHASE INPUT TRANSITION tPLH O UTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
Octal link
DISABLE 3V
CONTROL INPUT tPZL OUTPUT NORMALLY LOW SW ITCH CLO SED tPZH OUTPUT NORMALLY HIGH SW ITCH OPEN 3.5V 1.5V 0.3V tPHZ 0.3V 1.5V 0V tPLZ
1.5V 0V 3.5V VOL VOH
0V
Octal link
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
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IDT74FCT2573AT/CT FAST CMOS OCTAL TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX FCT XXXX Temp. Range Device Type X Package
SO Q PG
Small Outline IC Quarter-size Small Outline Package Thin Shrink Small Outline Package
2573AT 2573CT
Octal Transparent Latch
74
- 40C to +85C
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for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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